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SC9822P
MP3 DECODER WITH ESP FUNCTION AND CD INTERFACE
DESCRIPTION
SC9822P is a sing-chip Mp3 decoder with electronic shockproof function. It can be used in CD player, DISC-MAN and such systems which need MP3 decoder. And this chip provides smaller package, lower power dissipation and higher cost performance ratio.
FEATURES
* Provide ECC and EDC functions for CD-ROM data error correcting. * ISO/IEC 11172-3 L3 L2 L1 decode * ISO/IEC 13818-3 L3 L2 L1 decode * Support all MP3 bit rates and free formats under SO/IEC 11172-3 L3 L2 L1 specifications. * Support all MP3 bit rates and free formats under SO/IEC 13818-3 L3 L2 L1 specifications. * Support 48K/44.1K/32K MP3 standard sampling rate, 24K/22.05K/16K and 12K/11.025/8K low sampling rate * Support single/double/stereo/union stereo * Provide 16: 4, 16: 5, 16: 6 and non-compression four compression modes * Provide 3 pairs data, 2 pairs data and direct comparison connect three comparison connect modes. * Serial host interface * Support CD-DA straight through mode * Support SDRAM/DRAM interface * Only one external 16.9344MHz crystal oscillator * Power management: normal mode, brownout mode and dormancy mode * Various playing functions: skip forward/backward in track, skip forward/backward between tracks, pause, play and so on. * Support the file systems in ISO9660, Joliet and UDF formats * Support 1M/4M/8M/16Mx16 SDRAM, 1M/4M x16 DRAM
LQFP-64-10x10-0.5
ORDERING INFORMATION
Device SC9822P Package LQFP-64-10X10-0.5
APPLICATIONS
* Desk-top audio * Portable CD/Mp3 player * Car audio
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SC9822P
BLOCK DIAGRAM
ABSOLUTE MAXIMUM RATINGS
Characteristics Kernel Voltage Port Voltage Input Voltage on pins Ambient Temperature Storage Temperature Symbol VCCInt VCCIO VIN Tamb Tstg Rating 1.4 ~ 2.3 2.9 ~ 4.2 -0.3 ~VCCIO + 0.3 -20~90 -60~150 Unit V V V C C
ELECTRICAL CHARACTERISTICS (VCCINT=1.8V, VCCIO=3.3V, Tamb=25C)
Characteristics Kernel Voltage Port Voltage Quiescent Current Operating Current Operating Frequency Operating Operating Symbol VCCInt VCCIO IDDInt IDDIO ICCInt ICCIO MClk Test Conditions Normal working Normal working Kernel VDD1.8 supply current Port VDD3.3 supply current Kernel VDD1.8 supply current Port VDD3.3 supply current -Min. 1.6 3.1 --10.1 1.3 -Typ. 1.8 3.3 5.3 0 --16.9344 Max. 2.0 3.9 --11.9 2.5 -Unit V V A A mA mA MHz
(To be continued)
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SC9822P
(Continued) Characteristics High Voltage Low Voltage High Current Low Current High Low Level Level Output Output Output Voltage Voltage Tri-State leakage current Output Short Circuit Current Level Input Level Input Level Input Level Input Symbol VIH VIL IIH IIL VOH VOL IOZ IOS --Type anote Type anote IOH=1mA IOH=2mA IOL=1mA IOL=2mA VOUT=VSS or VDD VDD=3.3V, VO=VDD VDD=3.3V, VO=VSS Test Conditions Min. 2.1 -VIN=VDD VIN=VSS 0 0 ----0 --Typ. ----3.29 3.28 0.02 0.04 -47 35 Max. -0.6 ---------Unit V V A A V V A mA
Note: Type a: Common input port; Type b: Input port with pull-up resistor
PIN CONFIGURATION
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SC9822P
PIN DESCRIPTION
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 Pin name Addr<4> Addr<5> Addr<6> Addr<7> Addr<8> Addr<9> VDD3.3 Addr<10> Addr<11> SClk CKE BankSelect<0> VSS VDD1.8 BankSelect<1> NotWE NotRAS NotCAS VDD1.8 NotCSArray<0> DQ<0> DQ<1> DQ<2> DQ<3> DQ<4> VDD3.3 DQ<5> DQ<6> VDD1.8 VSS DQ<7> DQ<8> DQ<9> DQ<10> DQ<11> DQ<12> DQ<13> DQ<14> I/O O O O O O O I O O O O O I I O O O O I O I/O I/O I/O I/O I/O I I/O I/O I I I/O I/O I/O I/O I/O I/O I/O I/O Pin description SDRAM/DRAM address pin 4 SDRAM/DRAM address pin 5 SDRAM/DRAM address pin 6 SDRAM/DRAM address pin 7 SDRAM/DRAM address pin 8 SDRAM/DRAM address pin 9 Port supply voltage (3.3V) SDRAM/DRAM address pin 10 SDRAM/DRAM address pin 11 16.9344M SDRAM/DRAM clock output pin SDRAM/DRAM clock enable output pin SDRAM/DRAM block selecting output pin 0 Ground Kernel supply voltage (1.8V) SDRAM/DRAM block selecting output pin 1 SDRAM/DRAM write output pin which is a low active. SDRAM/DRAM row address strobe pin which is a low active. SDRAM/DRAM column address strobe pin which is a low active. OTP download voltage. SDRAM/DRAM chip selection output 0 which is a low active. SDRAM/DRAM data pin 0 with internal pull-up resistor. SDRAM/DRAM data pin 1 with internal pull-up resistor. SDRAM/DRAM data pin 2 with internal pull-up resistor. SDRAM/DRAM data pin 3 with internal pull-up resistor. SDRAM/DRAM data pin 4 with internal pull-up resistor. Port supply voltage (3.3V) SDRAM/DRAM data pin 5 with internal pull-up resistor. SDRAM/DRAM data pin 6 with internal pull-up resistor. Kernel supply voltage(1.8V) Ground SDRAM/DRAM data pin 7 with internal pull-up resistor. SDRAM/DRAM data pin 8 with internal pull-up resistor. SDRAM/DRAM data pin 9 with internal pull-up resistor. SDRAM/DRAM data pin 10 with internal pull-up resistor. SDRAM/DRAM data pin 11 with internal pull-up resistor. SDRAM/DRAM data pin 12 with internal pull-up resistor. SDRAM/DRAM data pin 13 with internal pull-up resistor. SDRAM/DRAM data pin 14 with internal pull-up resistor. (To be continued)
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SC9822P
(Continued) Pin No. 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 Pin name DQ<15> DacWs DacBck DacSd DacSysClk Ws Bck Sd VDD3.3 XALTI XALTO NotExtAsyncReset TestMode VSS VDD1.8 SsiSClk Data DataAvail YFCLK YBLKCK YFLAG InterruptToMcu Addr<0> Addr<1> Addr<2> Addr<3> I/O I/O O O O O I I I I I O I I I I I I/O I I I I O O O O O Pin description SDRAM/DRAM data pin 15 with internal pull-up resistor. Word selection clock pin output to DAC. Bit clock pin output to DAC. Data pin output to DAC. System clock output to DAC. Word selection clock input pin of CD-DSP. Bit clock input pin of CD-DSP. Data input pin of CD-DSP. Port supply voltage (3.3V). Oscillator input pin. Oscillator output pin. System reset pin which is a low active. Test mode pin which is a high active and connected to ground when it is not in test mode. Ground Kernel supply voltage (1.8V) MCU clock input pin. MCU data pin. MCU telecommunication control pin. Sync signal of sub code frame. Sync signal of sub code block. CD servo error flag. Interrupt pin which is a high active and output to MCU. SDRAM/DRAM address pin 0 SDRAM/DRAM address pin 1 SDRAM/DRAM address pin 2 SDRAM/DRAM address pin 3
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SC9822P
FUNCTION DESCRIPTION
1. CD/MP3 Register function Register description (The register address of SC9822P is 8 bits) Symbol Address Read/write Initialization Description Total time' minutes of current playing s music:0-59 Total time' seconds of current playing s music:0-59 Already played time' minutes of s current music:0-59 Already played time' seconds of s current music: 0-59 bit[3:0]: Sampling rate of current playing music 0x0: 44.1KHz 0x1: 48KHz 0x2: 32KHz 0x4: 22.05KHz 0x5: 24KHz 0x6: 16Khz 0x0C: 11.025KHz 0x0D:12KHz 0x0E:8KHz Reserve the rest; When the music format is Layer III: FrameInform[7:0] 0x65 R 0x03 Bit [7:4]: The bit rate of current playing music, together with sampling rate to decide current bit rate. This chip provides variable bit rate and free bit rate (*1). When the sampling rate is 44.1, 48, 32KHz, the other sampling rate is: 0x0: Free mode 0x1: 32kbps 0x2: 40kbps 0x3: 48kbps 0x4: 56kbps 0x5: 64 kbps 0x6: 80 kbps 8kbps 16kbps 24kbps 32 kbps 40 kbps 48 kbps (To be continued) SC9822P play state registers TotalTimeMin[5:0] TotalTimeSec[5:0] CurrentTimeMin[5:0] CurrentTimeSec[5:0] 0x61 0x62 0x63 0x64 R R R R 0x00 0x00 0x00 0x00
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SC9822P
(Continued) Symbol Address Read/write Initialization Description 0x7: 96 kbps 0x8: 112 kbps 0x9: 128 kbps 0x0A: 160 kbps 0x0B: 192 kbps 0x0C: 224 kbps 0x0D: 256 kbps 0x0E: 320 kbps 0x0F: Forbid When the music format is Layer I: 0x0: Free mode 0x1: 32kbps 0x2: 64kbps 0x3: 96kbps 0x4: 128kbps 0x5: 160 kbps 0x6: 192 kbps 0x7: 224 kbps 0x8: 256 kbps 0x9: 288 kbps 0x0A: 320 kbps FrameInform[7:0] 0x65 R 0x03 0x0B: 352 kbps 0x0C: 384 kbps 0x0D: 416 kbps 0x0E: 448 kbps 0x0F: Forbid When the music format is Layer II:(Nonsupport single channel mode) 0x0: Free mode 0x1: Nonsupport 0x2: Nonsupport 0x3: Nonsupport 0x4: 64kbps 0x5: Nonsupport 0x6: 96 kbps 0x7: 112 kbps 0x8: 128 kbps 0x9: 160 kbps 0x0A: 192 kbps 0x0B: 224 kbps 0x0C: 256 kbps 0x0D: 320 kbps 0x0E: 384 kbps 0x0F: Forbid (To be continued) 56 kbps 64 kbps 80 kbps 96 kbps 112 kbps 128 kbps 144 kbps 160 kbps
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SC9822P
(Continued) Symbol Address Read/write Initialization Description SC9822PC02 operating mode: Bit0: HostMemoryOpEnable 0b0: Disable Host operate external Sdram 0b1: Enable Host operate external Sdram Bit1: Mute 0b0: the current play is in the normal mode 0b1: the current play is in the mute mode Bit2: Pause 0b0: the current play is in the normal mode 0b1: the current play is in the pause mode StereoMode[7:0] 0x66 R 0x00 Bit3: Sleep 0b0: the current play is in the normal mode 0b1: the current play is in the sleep mode Bit4: MusicWillStart 0b0: no music playing 0b1: the music will output after 100ms delay. Bit5: Stereo mode 0x0: Single channel 0x1: Stereo Bit[7:6]: Mpeg music file 11: Layer I 10: Layer II 01: Layer III 00: reserved (To be continued)
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SC9822P
(Continued) Symbol Address Read/write Initialization Bit[7:4]: 0b0000: Idle state 0b0001: PreDecode state 0b0010: NormalPlay state 0b0011: FastForward state 0b0100: FastBackward state Others: Reserved CdrMode[7:0] 0x67 R 0x00 CD-ROM format: bit2: 0: Mode-1 1: Mode-2 bit1: Effective when bit2=1: 0: Form1 1: Form2 SC9822P state register: Bit[3:0]: 0000: Invalid state, no response 0001: ConfigFinished 0010: FileSystemFinished 0011: PreDecodeFinished 0100: SongEnd 0101:Fast backward to the first song 0110: OperationErr, error occurs, need host to process. 0111: FatalErr, serious error, require the host jump to the next song StatusReg[7:0] 0x60 R 0x00 1000: GetMaxPhysicalMSF, already received the max. physics address of the CD. Others: Reserved Bit[5:4]: 0b00: Invalid state 0b01: RequestData, apply for download new data 0b10: IntoCapture Bit6: 0b1: DownloadFinished, finish one time download. Others Reserved (To be continued) Description SC9822P state register:
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SC9822P
(Continued) Symbol Address Read/write Initialization Description The high 8 bits of general purpose register. The low 8 bits of general purpose register. The high 8 bits of general purpose output register. The low 8 bits of general purpose output register. The high 8 bits of general purpose input register The low 8 bits of general purpose input register The high 8 bits of general purpose input register 2 The low 8 bits of general purpose input register 2 HOST sends to internal control command register, HostMcuCmd[7:0] 0x01: StartConfigure 0x02: SetUpCDFS 0x03: DecodeMp3 0x04: ContinueAfterPreDecode 0x05: Fast Forward 0x06: Fast Backward 0x07: Resume 0x08: Pause HostMcuCmd[7:0] 0x70 W 0x00 0x09: Stop 0x0A: Soft Mute On 0x0B: Soft Mute Off 0x0C: CDDA Through 0x0D: ForwardSkipFrame (*2) 0x0E: StartCapture CDITF 0x0F 0x11:Reserved 0x12: Mem Read Write Request 0x13: Mem Read Write End 0x14: SystemSleep 0x15: SystemWakeUp 0x16: Reserved (To be continued) HOST and internal registers which control the communication OutReg2High[7:0] OutReg2Low[7:0] OutRegHigh[7:0] OutRegLow[7:0] InpRegHigh[7:0] InpRegLow[7:0] InpReg2High[7:0] InpReg2Low[7:0] 0x68 0x6C 0x69 0x6A 0x71 0x72 0x73 0x74 R R R R W W W W 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
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SC9822P
(Continued) Symbol Address Read/write Initialization Description 0x17: TestMode 0x18: PcmStart 0x19: PcmStop HostMcuCmd[7:0] 0x70 W 0x00 0x1b: SetUpCDFS2 0x1c: GetVersion 0x1d: SetMaxPhysicalMSF Others: Reserved External interface control registers External SRAM/DRAM type: bit4 = 1, SDRAM type bit[3:0]: 0000:1BANK*(4096*256 => 1M*16) 0001: 2BANK*(2048*256 => 512K) 0100: 2BANK*(4096*512 => 2M) 0101: 4BANK*(4096*256 => 1M) 0110: 2BANK*(4096*1024 => 4M) 0111: 4BANK*(4096*512 => 2M) 1000: 4BANK*(4096*1024 => 4M) HramType[4:0] 0x75 W 0x00 Reserve the rest When bit4 = 0, Dram type bit[3:0]: 0110:4M * 16bit(4K*1K*16) (4k ref) 0101:4M * 16bit(8K*512*16) (8k ref) 0100:1M * 16bit(1k*1k*16) (1k ref) 0011:1M * 16bit(2k*512*16) (4k ref) 0010:1M * 16bit(4k*256*16) (4k ref) 0001:256k*16(512*512*16) Reserve the rest bit[3:2] is the input interface of CD-DA, bit[1:0] is the output interface of DAC(*3) bit3: 1: Input is IIS interface 0: Output is EIAJ interface bit2: BitStreamType[5:0] 0x76 W 0x00 0: Input word clock has 16 bitclk 1: Input word clock has 24 bitclk bit1: 1: Input is IIS interface 0: Output is EIAJ interface bit0: 0: Output word clock has 16 bitclk 1:Output word clock has 24 bitclk (To be continued)
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SC9822P
(Continued) Symbol CdRomType Address 0x77 Read/write Initialization Bit[0]: W 0x00 1:CD-ROM XA format disk 0:Common CD-ROM format disk Read external RAM registers MemAddrHigh[7:0] MemAddrMid[7:0] MemAddrLow[7:0] 0x7A 0x7B 0x7C W W W 0x00 0x00 0x00 High 8 bits of start address when external RAM outburst method to read Middle 8 bits of start address when external RAM outburst method to read Low 8 bits of start address when external RAM outburst method to read External RAM read-write command register MemCmd[7:0] 0x7D W 0x01 Bit[7:0]: 0x00: External RAM read command 0x80: External RAM write command Note: 1. when it is in free mode, do not displays the bit rate of current music in FrameInform register. At this time, the display time may be wrong. 2. ForwardSkipFrame is when occurs error, if CD-DSP can not ensure the position of M.S.F needed by SC9822P, Host denotes SC9822P to skip the number of Second and Frame. Hereinto, the number of second is stored in InpRegHigh(8' h71), and the number of Frame is stored in InpRegLow(8' h72). 3. The interface data of DAC and word clock are changing at the falling edge of the bit clock. 2. CD/MP3 Exchange with Host The general purpose register provides parameter for main control command, and output register together with state register provide some parameters: 1) StartConfigure InpRegHigh&InpRegLow is a 16 bits unsigned number, if the blank data CdItf input to the buffer is larger than this threshold, it will startup the next download operation; through configuring this value, the Mp3 shockproof time and CD pick up head jump frequency can remain balance; the value has an effective range related with SDRAM configuration; If the input value exceeds the enable range, the default value will replace the input value; Before send StartConfigure, the main controller will configure the HramType BitStreamType and CdRomType. 2) SetUpCDFS InpRegHigh, InpRegLow, InpReg2High are file start MSF physics address respectively; InpReg2Low is the number of folders required (the maximum value is 0xFF). During file building, if operation occurs error, the Host can repeat sending SetUpCDFS command; when file system is finished, the OutReg1High&OutReg1Low indicate music file number; if the file number is 0, it means the file system cannot be finished. Description
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SC9822P
3) DecodeMp3 InpRegHigh&InpRegLow is 16 bits unsigned number, indicate the playing music file number; InpReg2High is an 8 bits unsigned number, indicate whether this music needs ID3 decode; 4) PreDecodeFinished OutReg1High&OutReg1Low, 16 bits unsigned number, is used to indicate the ID3 start page address in the process of PreDecode after ID3 decode; OutReg2High, 8 bits unsigned number, ID3 shift address; If these three registers are all 0xFF, this song will not contain ID3 information; 5) ContinueAfterPreDecode After host detects the PreDecodeFinished, the system will send command for playing music; and the host has read the ID3 information before send command. 6) FastForward InpReg1High, is used to express the second of each fastforward unit; InpReg1Low, is used to express the fastforward ratio, the detail see the following table: InpRegHigh play time(s) Not support others InpRegLow Skip scale 00h 1:1 01h 1:2 02h 1:4 03h 1:8 00h 0.5 10h 1 20h 2 30h 4
Skip scale is the ratio of play time and leap time. 7) FastBackward InpReg1High, is used to express the second of each fastbackward unit; InpReg1Low is used to express the fastforward ratio; Where the meanings of InpRegHigh is the same as fastforward; but the InpRegLow is different, it expresses n of the play time: skip time=1: n. 8) RequestData OutReg1High, OutReg1Low, OutReg2High are the MSF of download address; 9) OperationErr Except SetUpCDFS, if host detects the OperationErr at other state, it will send ForwardSkipFrame command; if the host received this command time after time during one song, it indicates this song has been serious damaged; it can jump to the next song. 10 SetUpCDFS2 Establish the tile document system; the meanings of the input and output parameter is the same as SetUpCDFS; 11 GetVersion Return to the current version number, OutRegHigh is the main version number, and the OutRegLow is the vice version number. 12 SetMaxPhysicalMSF The master indicates the SC9822P the maximum physical address of the CD by this command. The registers InpReg1High, InpReg1Low, and InpReg2High are corresponding to MSF value;
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SC9822P
3. CDFS Tables CDFS Table impropriate 351page 351*256*16bit , the default address is the highest part of external RAM, 0xxEA0-0xxFFF(Page address), the following figure is the configuration in the RAM:
If RAM is 1M*16bit, z is 0; if RAM is 2M*16bit, z is 1; if RAM is 4M*16bit, z is 3; if RAM is 8M*16bit, z is 7; if RAM is 16M*16bit, z is F. File configuration: Address Introduction Table (1 page) 0xxEA000(16bit) 0xxEA001(16bit) 0xxEA002(16bit) 0xxEA003(16bit) 0xxEA004(16bit) Directory Table(4 pages 8bit 8bit 16bit 16bit 8bit 8bit 32bit 32bit 16bit 16bit 32bit 128Byte 128Byte Total folder number in CD Total mp3 file in CD Total mp3 folder in CD The folder no. of the first mp3 file Including mp3 file number (each folder) The start folder no. of this directory The folder number of this directory The started mp3 file no. of this directory Total Mp3 file number of this directory Parent directory no. Folder name length M.S.F information of Mp3 file The size of Mp3 file The length of Mp3 file name Mp3 file type Reserved Folder name Mp3 file name Contents
File Table (32 pages) (each file)
Directory Identifier Table (64 pages) File Identifier Table (250 pages) Maximum file number is 1024, and the maximum folder number is 256 supported.
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SC9822P
4. ESP Register description Symbol Esp control register Bit[0] : Control Esp operation mode 0-> straight in mode 1->electronic shockproof mode Bit[1] : 0-> Esp enable 1-> Esp disable Note: In the normal Esp operation, each time write to MSC80H, this bit should be set to 0. Bit[3:2]: Compare and connect command 00-> stop command 01-> execute command 10-> 2 pairs of commands 11-> 3 pairs of commands Note: During the compare and connect, if receive the new command, it will execute according the new command; and if receive the stop command, it will exit the compare and connect operation, and not output any result. MSC80H [7:0] 0x50 W 0x00 Bit[4] : LocalReset command 0-> NOOP 1->reset the codec Bit[5] : Decode start command 0-> decode disable, 1-> decode enable. Bit[6] LocalReset command Address R/W Initialization Description
0-> NOOP 1->reset the codec Bit[7] : Encode start command 0-> stop encode 1-> start encode Note: When the compare& connect command and encode start command occur at the same time, the compare & connect command have the high PRI. If the encode command occurs in the compare & connect process, it will execute command. (To be continued) the compare and connect
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SC9822P
(Continued) Symbol Address R/W Initialization 0-> NOOP 1-> mute operation Bit[6:5] : Set compare & connect modes 00-> 16-bit precision MSC83H [7:0] 0x51 W 0x00 01-> 12-bit precision others-> 8-bit precision Bit[7] : WAQV signal, is the data valid signal send by MCU. 0-> NOOP 1-> data enable, execute the Valid operation Bit[3:0] : Encoder operation modes 1000-> non-compress mode, the audio data not compressed, and enter DRAM buffer directly 0100-> 6-bit compress mode 0010-> 5-bit compress mode 0001-> 4-bit compress mode others-> 6-bit compress mode, this is the default mode. Bit[5:4]: CD shock signal detect modes 00-> YFCKP falling edge, YFLAG 0, judge it is shock 01-> YFCKP rising edge, YFLAG 0, judge it is shock 10-> YFLAG 0, judge it is shock 11-> YFLAG = 1, judge it is shock Bit[6]: SBSY sync modes 0-> SBSY falling edge sync, execute the Latch operation 1-> SBSY rising edge sync, execute the Latch operation Note: The default mode is 0. Esp status register Bit[1]: Decoder stop because the internal reason. 0-> decoder normal operation, (Encoder MSC90H [7:0] 0x53 W 0x00 local reset, register execute the read/write operation, external reset). 1-> decoder stop because the internal reason, (detect the remain valid data is 0). (To be continued) Description Bit[3] : Mute control signal
MSC85H [7:0]
0x52
W
0x00
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SC9822P
(Continued) Symbol Address R/W Initialization Description Bit[2] : Encoder stop because the internal reason. 0->encoder normal operation (compare & connect complete, encoder local reset, external reset). 1->Encoder stop because the internal reason (FLAG6, BOVF, MSOVF are set). Bit[3]:Compare and connect operation symbol : 0->not connect the coding (compare & connect complete, compare & connect stop, external reset), 1->execute the coding connect operation (compare & connect command). Note: During the compare & connect, send the encoder start command, it is equal to send compare & connect command directly. So there MSC90H [7:0] 0x53 W 0x00 can clear the compare & connect symbol. Bit[5] :Input buffer overflow symbol. 0-> input buffer normal, (this register read operation, codec local reset, external reset) 1->input buffer overflow, (input buffer overflow). Bit[6]: External DRAM write overflow symbol. 0-> external DRAM normal write, (this register read operation, codec local reset, external reset). 1-> external DRAM write overflow Bit[7]: Shock symbol. 0-> normal operation, no shock, (this register read operation, Esp operation mode from straight in switch to shockproof mode, external reset). 1-> CD shock, (detect the CD vibrate) SC91H [7:0] Note: The flag of this register state denotes signal; if the the 0x54 R 0x00 Note: In normal, Restore operating time is very short, so this signal should remain 0. (To be continued) Bit[2] : Restore status signal 0-> the current Restore operation not execute(have been completed) 1-> Restore is operating
status is not satisfied, the corresponding bit will clear automatically.
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SC9822P
(Continued) Symbol Address R/W Initialization Description Bit[3] : LocalReset status signal 0-> none LocalReset operation 1-> LocalReset operating Note: In normal, LocalReset operating time is very short, so the status signal should remain 0. SC91H [7:0] Note: The flag of this register state denotes signal; if the the 0x54 R 0x00 Bit[4]: Decoder operation status signal 0-> decoder stop 1-> decoder operate Bit[5]: Encoder operation status signal: 0-> encoder stop, 1-> encoder operate Bit[6]: Dram overflow symbol 0-> Dram in normal 1-> Dram overflow Bit[7]: Dram empty symbol 0-> Dram have valid data supply for decoder, 1-> Dram empty, no valid data supply for decoder. Bit[7:0]: The remain valid data in DRAM take MSC92H High[7:0] 0x55 R 0x00 page as unit. The high 8 bit data, each page is 256x16bit. Bit[7:0]: The remain valid data in Dram take page as unit, there is the low 8 bits, each page is 256x16bits. MSC92HLow [7:0] 0x56 R 0x00 Note: because the 16-bit pointer is divided two parts for read operation, in the reading, the pointer also operating, so we should notice the carry bit in reading operation of main control processing. Esp configuration register BitPoolPageLimitHigh and BitPoolPageLimitLow form the up limit of DRAM, and determined the DRAM space as BitPoolPageLimitHigh [7:0] ESP buffer; 0x58 W 0x07 Note: the external DRAM space of BitPool address which can be accessed by BitPool is Page[0, BitPoolLimitHigh & BitPoolPageLimitLow]. In the current MCU design, each page is 256x16bit (To be continued)
status is not satisfied, the corresponding bit will clear automatically.
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(Continued) Symbol BitPoolPageLimitLow [7:0] Address 0x59 R/W W Initialization 0xff Shock signal ShockMsk[7:0] 0x5B W 0x00 shield register. Its unit is Description
128*59ns=7.552us, if the signal length is less than input time, it is not consider the shock. The max. shock shield time is 255x7.552us = 1,925.880 us. Register in the Mmu module Bit[2:0]: Control the Sdram operation. 0 >no operation 1 >control Sdram carry out Precharge 2 >control Sdram carry out CBR 3 > control Sdram set modes 4 >enable Sdram controllable refresh 5 >disable Sdram controllable refresh, but enable Sdram auto refresh. When Sdram not used in a period, but there should remain the data, it can adopt this mode, then reduce the power dissipation. 6-- >DRAM SELF-REFRESH MODE, only for " version dram. When enter this s" mode for more than 100us, DRAM will be in SELF-REFRESH state. you can change mode only by set MmuHostCmd MmuHostCmd[7:0] 0x00 RW 0x08 BIT[2:0] to 7(that' change to normal s mode of dram) 7-- > DRAM NORMAL MODE, before read or write operation of DRAM, you should enter NORMAL MODE for 200us for DRAM initialization (auto execute internal 8 cycles of refresh to initiate dram device) Bit[3] : Enable Sdram initialization 0 > enable Sdram initialization, and do it in the control of Bit[2:0] 1 > disable Sdram initialization, *-- > for DRAM, this bit is not care Bit[7:4] When use sdram, Bit[7:4] select Sdram type 0000 1BANK*(4096*256 => 1M*16) 0001 2BANK*(2048*256 => 512K) (To be continued)
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(Continued) Symbol Address R/W Initialization Description 0100 2BANK*(4096*512 => 2M) 0101 4BANK*(4096*256 => 1M) 0110 2BANK*(4096*1024 => 4M) 0111 4BANK*(4096*512 => 2M) 1000 4BANK*(4096*1024 => 4M) 1001 4BANK*(8192*512 => 4M) when use dram, Bit[7:4] select dram type: 0110 4M * 16bit(4K*1K*16) (4k ref) MmuHostCmd[7:0] 0x00 RW 0x08 0101 4M * 16bit(8K*512*16) (8k ref) 0100 1M * 16bit(1k*1k*16) (1k ref) 0011 1M * 16bit(2k*512*16) (4k ref) 0010 1M * 16bit(4k*256*16) (4k ref) 0001 256k*16(512*512*16) * Note: for dram, access timing of 50ns and 60ns dram are supported, 70ns haven' been tested. t CompareDataBaseAdd ressHigh [7:0] CompareDataBaseAdd ressLow [7:0] G722StatusBaseAddre ssHigh [7:0] G722StatusBaseAddre ssLow [7:0] 5. ESP Program Guide 5.1 Enter Esp Mode First send short command 0x04, then enter Esp mode. 100: 011: EspMode UnEspMode (Enter Esp mode command) (Exit Esp mode command) 0x02 0x03 0x04 0x05 RW RW RW RW XX XX XX XX Store the page base address Bit15 compare & connect data. Store the page base address Bit7 compare & connect data. Store the page base address Bit15 G722 status data. Store the page base address Bit7 G722 status data. Bit0 of Bit8 of Bit0 of Bit8 of
5.2 Configure external Sdram HOST need to initialize Sdram. Send the command 0x51 0x52 0x52 0x53 0x54 0x50 0x58 to register MmuHostCmd(8' h00) in turn. Host initialized Dram. Send the command 0x47 to register MmuHostCmd(8' h00) HOST need to configure the address of comparative data and decoding information. Send the command 0x0f to register CompareDataBaseAddressHigh (8' h02), send the command 0xf4 to register CompareDataBaseAddressLow (8' h03), send the command 0x0f to register G722StatusBaseAddressHigh (8' h04) and send the command 0xf8 to register G722StatusBaseAddressLow (8' h05). HOST need to configure the size of Sdram. Now it can only support page as unit, BitPoolPageLimitHigh(8' h58) BitPoolPageLimitLow(8' h59) .
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5.3 Configure audio input and output interface HOST need to configure audio input interface. The input and output are 24 Bitclk of IIS interface. Send the command 0x0f to register BitStreamType (8' h76). 5.4 Configure compress mode, shake detecting mode, and shake signal shield time HOST need to configure the compress mode. There are 4 compress modes to be selected (16: 4 compress, 16:5 compress, 16:6 compress and non-compress), which will send the command to register MSC85H(8' h52). HOST need to configure the shake detecting mode. There are 4 modes to be detected(rising edge of sub block sync signal, shake signal low level determinant; falling edge of sub block sync signal, shake signal high level determinant; shake signal low level determinant; shake signal high level determinant), Send the command to register MSC85H(8' h52). HOST can configure shake signal shield time. Because Cd servo only receives some very short level jam signal, but not the signal we need, we can solve this problem by setting the shake signal shield time. Send the shielded time to register (8' h5b), the unit is 128*59ns=7.552us, the length of shake signal within the input value, it will not be considered as shake signal. The maximum shake shield time is 255x7.552us = 1,925.880 us. 5.5 Begin to encode and decode HOST sends encoding start command. Send 0xa1 to register MSC80H (8' h50). 5.6 Read Q sub code Read Q sub code of Cd every other time, and if the Q sub code is not continuous, do not enter Esp control flow, delay and read again. if the Q sub code is continuous, enter Esp main control flow. 5.7 Adopt query method to detect the state HOST will send query command every other time. Read register MSC90H (8' h53). 5.8 Send WAQV signal HOST sends affirm command of effective signal. When the state is normal, send the command 0x80 to register MSC83H (8' h51), and record the current effective address of Q sub code. 5.9 Send the compare& connect command When read the three abnormal states of shake signal, input buffer overflow and Sdram data overflow, take CD back according to the effective address of Q sub code. Then begin to compare& connect to correct data. HOST configures the compare&connect command. There are 3 methods (16-bit, 12-bit, 8-bit precision). Send the command to register MSC83H(8' h51). HOST sends the compare & connect start command. There are two methods(3 pairs data comparative, direct compare & connect). Send the command to register MSC80H(8' h51).
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6. Power Management Description SC9822P has PowerDown, Running and Sleep three working mode: PowerDown: Sleep: Running: Close the system oscillator The oscillator of chip is not closed, but the working main clock is closed, and refreshes the SDRAM/DRAM periodically. Normal working mode
The command used for controlling the power supply is the short command format referred in SSI command interface: The specific command of Host is 2 bytes, whose format is: DevCmd[7:0]: HostCmd[7:0], thereinto, DevCmd[7:4]=" 0110" is specific byte, DevCmd[3:0] is still denoted receiving the Guest' address of this s command. The specific command of HostCmd is: HostCmd[2:0]: 000: 111: 001: 110: 010: 101: 101: PwrReset UnPwrReset PowerOn PowerOff Sleep WakeUp WakeUp (Software reset command. The chip is in the reset state once the command is sent out, and release the reset state until Host sends the releasing reset command) (software release reset command) (software power on command) (software power off command) (enter Sleep state) (exit Sleep state) (exit Sleep state)
System power on: Host sends HostCmd: PwrReset(0x0)command, make the system in reset state; Host sends HostCmd: PowerOn(0x1)command, start the system oscillator ( or make the external clock into SC9822P), and after a time (7 10 clock cycles), the main clock is into the system; Host is waiting for a time (wait until OSC clock is in the stable state, about 100ms), and then sends HostCmd: UnReset(0x7)command, make the system exit the reset state, and prepares to receive the Host' normal commands. s System power off: Host sends HostCmd: PwrReset(0x0)command, making the system in reset state; Host sends HostCmd: PowerOff(0x6)command; The system is in power off state.
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System standby (Sleep): Sleep command starts at the Pause stage; Host sends HostCmd: Sleep(0x2)command; Host sends system standby command (SystemSleep:0x31)to HostMcuCmd(8' h70); After a time, the system comes into standby state, but it will time-lapse refresh SDRAM/DRAM, and protect the data of SDRAM/DRAM from losing. System recovery (WakeUp): Host sends HostCmd: WakeUp(0x5)command, exit the Sleep state; Host sends SystemWakeUp command (0x32) to HostHostCmd(8' b70)to start the system after waiting for about 5 ms; Host waits for 5 ms to return to normal working state.
TYPICAL APPLICATION CIRCUIT
DacBck
YFLAG
DacSyClk
YBLKCK
YFCLK
NotCSArray (0)
DacWs
DacSd
InterruptTo MCU
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DataAvail
NotRAS
NotCAS
NotWe
DQ(15)
CKE
Addr11
DQ(0)
Addr0
Sclk
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SC9822P
SC9822P EXTERNAL MEMORY DIAGRAM
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PACKAGE OUTLINE
LQFP-64-10x10-0.5
Unit: mm
10.00.1
12.00.2
11.0
HANDLING MOS DEVICES: Electrostatic charges can exist in many things. All of our MOS devices are internally protected against electrostatic discharge but they can be damaged if the following precautions are not taken: * Persons at a work bench should be earthed via a wrist strap. * Equipment cases should be earthed. * All tools used during assembly, including soldering tools and solder baths, must be earthed. * MOS devices should be packed for dispatch in antistatic/conductive containers.
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ATTACHMENT INTERFACE FUNCTION DESCRIPTION
1. Interface to main control MCU SC9822P communicates with host computer' MCU in synchronism serial bus (SSI) data interface of our s company. 1.1 Serial interface signal form The serial interface communicating with MCU has 3 signal lines including control signal, data signal, and the sequence is as followed:
Thereinto, SsiSClk is the clock generating from Host port, and the frequency can rebound in a wide range (as long as the wave is not distortion), and is independent with Guest port; DataAvail used for marking effective data time quantum is also sent by host computer and it is a low active; Data is a bidirectional signal with pull-up resistor and used for specific data communication and feedback. As above picture, the data sent by the host port is all at the falling edge of SsiSClk and the feedback data or Ack signal of guest port are at the rising edge. We define one transmitting process as a frame, and the details of the coherent signal are as followed: Start Signal: Start of frame We define the first checking low level of DataAvail at the rising edge of SsiSClk at Guest port as the start of frame. When check the start signal, the guest can receive the data at the next rising edge. Data Signal: Ack: Data signal Data signal bit wide sent by host computer is one SsiSClk clock cycle. Feedback signal 1. When Guest port receives the right addressing data, it feeds back to Host signal. And the width is a SsiSClk cycle. Used for data lead avoiding unmatched signal between two rising edges or corresponding to the data feedback to Host. 2. When Host sends to all Guest ports, signal before sending data is as lead signal, and between two falling edges of SsiSClk. EndSignal: End of frame When Guest detects the DataAvail at rising edge of SsiSClk, it means the transmission is end and waits for the next one. 1. 2 Serial communication protocol processing Host and Guest realize the communication between each other by different explanation and processing for the data. The transmission process of one frame is as followed:
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Figure 1 SSI frame signal In the above transmission, Command pack explains the type of the frame; BurstLength suggests the data byte length (don' have this byte in non Burst mode); Addr is 8-bit address length. Data0~DataN is to define t the length of BurstLength; the leading Ack is given to Guest by Host (Customers address check all mode common), and may be fed back by Guest. That is all decided by the information of Command pack. Command: In the process of the whole protocol processing, the Command pack byte is critical. 8 bits of Command byte are as followed: Bit7 Read/Write Read/Write: Burst: Reset: Bit6 Burst Bit5 Reset Bit4 AddrExtend Bit3 Address[3] Bit2 Address[2] Bit1 Address[1] Bit0 Address[0]
Read-write flag bit; 1 denotes read data from Guest to Host, and 0 denotes the data flow is from Host to Guest. Denote it is whether in Burst mode; 1 denotes this mode, and the byte behind Command byte is used as denoting the Burst length. 1 denotes selected Guest reset, at this time, have no next byte; When Burst and Reset are 1 at the same time, denotes short command form. The form of short command is introduced in power management.
AddrExtend: Address[3:0]:
1 denotes this operation based on 16-bit address mode, and high 8-bit follows the low 8-bit; 0 is default 8-bit address operation mode. Assign the operation object. Note: When Address[3:0] = 4' b1111, all the Guests will be operation objects (common), but at this time , the Guest should close the feedback channel and only receive the data sending by Host. And when selected the only Guest, it can be bidirectional communication (respective).
BurstLength: Addr: Ack:
Denote the operation length of Burst. 8-bit addressing address of Host. It is an acknowledge signal. In the address check all modes; this signal is only used as leading data (low level) to denote the beginning of the data pack because the feedback channel of Guest is closed. In one-to-one mode, After the Guest receives a serial of pack leading with Command byte; it must feed back to Host an Ack signal in defined time which is decided by Host itself. When sending the data, if the transmission direction is from Host to Guest this time, Guest must feed back an Ack signal in defined time every time it receives a data; if overstep, Host will pull up DataAvail and end this transmission. When Host sends the data, if there is other data needed transmission after Host receives the Ack signal, it must transmit following the next cycle; When Host receives data, it must come into receiving state (otherwise end this transmission directly) after Host receives the Ack signal.
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Data: The transmitted data is following the leading Ack signal, and the bytes of data are decided by BurstLength byte or Burst of Command. The former is used for Burst effective, and the latter limited a data when Burst is 0. When over the provision data, the receiver may not correspond to Ack signal. According to above description, if complete the operations from Host to Guest, different transmission patterns are as followed: Adopt non-Burst mode, 8-bit effective address, and assume the addressing address of guest is 0H:
Figure 2 Write flow of non-Burst mode
Figure 3 Read flow of non-Burst mode Adopt Burst mode, and suppose Burst Length = N, Guest addressing is 00H:
Figure4 Write flow of Burst mode
Figure 5 Read flow of Burst mode
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1. 3 SC9822P register read-write protocol A single register read command:
Thereinto, S is Start Signal, P is Stop Signal, DevReadCmd is read command (suppose Guest' s address is 1, and DveReadCmd is: 0x81), RegAddr is the address of the register, Waiting is the waiting time of Host, StartAddr is the address of start register when read constinuously. Constant register read command:
A single register write command:
Constant register write command:
1.4 Read-write Memory Protocol Read operation HOST originates one data read operation of SDRAM/DRAM; HOST sends Mem read-write application (0x12) to HostMcuCmd(8' h70); HOST waits for Mem read-write enable interrupt; HOST writes the start address of SDRAM/DRAM to MemAddrHigh(8' h7A), MemAddrMid (8' h7B), MemAddrLow (8' h7C) after read-write enable interrupt; and the read command(0x00) write to MemCmd(8' h7D); HOST originates data read operation, and appoints the number of the operation, the range is 2-255 bytes, and the default value is 2. Then read the data of BL*8bit (BL is the appointed value of BurstLength: MemDataBL, and is expressed as n+1= MemDataBL in figure 7); If HOST still need read data, repeat the above operation; HOST completes read operation, send Mem read-write end command (0x13) to HostMcuCmd(8' h70).
Figure6 Memory read operation Write operation HOST originates one data write operation of SDRAM/DRAM; HOST sends Mem read-write application (0x12)to HostMcuCmd(8' h70); HOST waits for Mem read-write enable interrupt;
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HOST writes the start address of SDRAM/DRAM to MemAddrHigh(8' h7A), MemAddrMid (8' h7B), MemAddrLow (8' h7C) after read-write enable interrupt; and the read command(0x80)write to MemCmd(8' h7D); HOST originates data write operation, and appoints the number of the operation, the range is 2-255 bytes, and the default value is 2. Then read the data of BL*8bit (BL is the appointed value of BurstLength: MemDataBL, and is expressed as n+1= MemDataBL in the following figure); If HOST still need write data to external RAM, repeat the above operation; after HOST completes read operation, send Mem read-write end command (0x13) to HostMcuCmd(8' h70).
Figure7 Memory write operation Note: 1. the memory read-write operation in figure 7and figure 8, it needs Waiting before every Ack signal; 2. every time read or write, it needs a specific register (8' h80) as the start address of Memory; 3. Only support 32 words (each word 16 bits) for Memory read-write addressing, that is to say every read-write begins with 32 times address value. 2. Interface with CD-DSP 1) 24-bit Bck, the MSB send first, and the data is right flush, the word selection signal of right channel is low (EIAJ-24)
2) 24-bit Bck, the MSB send first, and the data is left flush, the word selection signal of right channel is high (IIS-24)
3) 16-bit Bck, the MSB send first, the word selection signal of right channel is low (EIAJ-16)/ the word selection signal of right channel is high (IS-16)
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